1. Field of the Invention
The present invention relates to memory devices, and more specifically, to a method for efficiently multiplexing an internal RAM of a controller, and a free-block of non-volatile memory for managing a copy-back operation.
2. Background of the Invention
Most of the flash memories have an internal copy-back command available. However, some memories do not have this in-built feature, and require a usage of an external RAM of the flash memory controller. Thus the copy-operation can only be carried out by using the external controller's RAM. The copy-back is managed by reading data from a source, page by page, and then writing it to a destination in the same way. A large amount of RAM is required for temporarily storing the data between these read and write operations.
The existing techniques use a small part of RAM (almost 512 Bytes) for performing multiple read-write operations with multiple programming commands. This takes a longer time for the copy operation of several pages because the programming times, usually, are greater than a read and write time. Moreover, the area of the Look-Up Table (LUT) in the RAM is not utilized, and thus remains un-changed.
Another method to overcome this problem is to invalidate the LUT, while utilizing the LUT RAM area after copy-operation and later build the LUT again. However, this process is time consuming, as all blocks need to be read again and then a logical to physical mapping is re-built.
U.S. Pat. No. 6,760,805 discloses a flash management system for a large page size. The patent describes the usage of the 2K/Large Page size NAND for enabling flash memory systems to support flash devices with pages that are larger than operating system data sector sizes, while not describing the copy algorithm itself.
U.S. Pat. No. 6,978,342 discloses a technique to identify a source and destination location, when a decision is taken to copy a data from an “original location” to a “moved location”. Therefore, this method does not address the copy algorithm itself but only identifies the source and destination blocks.
U.S. Pat. No. 6,970,969 provides a multiple segment data structure and a method to manage data objects stored in multiple segments. However, this method does not address the algorithm technique for a copy operation.
U.S. Pat. No. 6,868,007 provides a controller system with a first decoder which decodes an address for a page copy destination and a data input command and controls the operations of a row decoder and a control circuit, a sense amplifier, and a page buffer. A second decoder decodes an address for an ordinary program and a data input command and controls the operations of the row decoder and control circuit. It also provides for a data copying method by inputting a management data for page data to a redundant area of a nonvolatile memory, executing a program, and when moving the page data in the nonvolatile memory to one other page, reading the page data during a program period for the one other page to check the page data for errors. Therefore, this method provides for a memory controller system with inbuilt decoders. However, it does not provide for a copy operation by sharing the look-up RAM memory.
U.S. Pat. No. 6,661,706 discloses an inbuilt facility, inside the memory itself, to manage a copy-operation within itself once the source and destination addresses are provided.
The prior art discussed above does not overcome all the shortcomings encountered in the field of copy back operation in the flash memories. Problems like a large processing time, failure to address a copy algorithm itself, failure to provide for a copy operation by sharing a look-up RAM memory, etc., still persist.
Therefore, there arises a need to provide an efficient copy operation in the flash memories. There is a need to provide a method for efficiently copying of data with utilizing a large size additional RAM There is a need to provide a method for efficiently copying of data with high throughput rates. There is a need to provide a method for efficiently copying of data in memories, which do not support internal copy back command.
The proposed method requires a lesser amount of RAM storage, which otherwise can be utilized for other purposes, and at the same time the method performs the task in a lesser amount of time as the transfer rate of copy operation of data from the one block to another is maximized by the method.